This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Synchronous dynamic random access memory (SDRAM) devices generally operate under a single external clock signal that is routed to a number of locations throughout the memory device. Synchronization of clock and data signals may be desirable to ensure proper operation of the memory device. By routing a single clock signal along a number of signal paths and to various associated circuitry, delays are introduced along each of the signal paths. As can be appreciated, each of the signal paths and associated circuitry may produce a different delay, and each delay can effect the synchronization and operation of the memory device.
One important timing requirement involves output data signals. The timing of when output data is made available or is clocked through the output buffer of the memory device is dependent on when valid data is available from the memory cell array. Specifically, in conventional systems, data output timing is determined by the access time (tAC) and the output hold time (tOH) of the SDRAM. To ensure valid data, the output data is synchronized to be clocked from the output buffer during the time interval between tAC and tOH. In certain SDRAM devices, data output is synchronized to the rising and/or falling edge of the system clock using a delay lock loop (DLL) for controlling the internal clock of the memory device so as to synchronize data output with the rising/falling edges of the external system clock. The DLL circuitry generally inserts delay time between the clock input buffer and the data output buffer thereby making the data switch simultaneously with the external clock.
During high speed operation of the memory device, accurate and timely adjusting of the delay units in the DLL may be difficult due to the stringent timing margin associated with the device. As can be appreciated, to provide optimal operation of the memory device, a receiving device should receive data no later than specified time (tAC) after the previous rising edge of the clock signal. Waiting a time (tAC) allows the input of a receiving device to stabilize before the next rising edge of the clock when the data is latched by the receiving device. Similarly, a transmitting device must continue to provide the data to the receiving device for a specified time (tOH) after the rising edge of the clock signal to ensure that the receiving device has completely latched the communicated data before the transmitting device removes the data from the bus. Timing and synchronization of the clock signals during high speed operation can be especially challenging for designers of memory devices.